As is commonly known, the path between the collector-base PN junction and the collector contact in a monolithic bipolar circuit has a high series resistance. To reduce this resistance in general, a conductive buried layer is provided between the substrate and the epitaxial layer containing the collector. Although N+buried layers are easily producible in vertical NPN devices, because of the high diffusion constant of P-type dopants, it is problematic to form P-type buried layers for vertical PNP devices. As a result, it is very difficult to manufacture complementary bipolar devices with both P and N-type buried layers.
One approach to fabricating complementary bipolar devices having an N+ buried layer is to use dielectric isolation (DI). In this process, anisotropically etched grooves are formed in a polished surface of N-type single crystalline silicon for separating later formed N and P type wells. P type dopants are then selectively diffused in the backside of the wafer to form the P type wells. Slow diffusion of N-type dopants such as arsenic is then selectively introduced in the N wells for forming the N+ buried layer.
In addition to the difficulty in producing a highly conductive P+ buried layer for the vertical PNP device, there are other disadvantages of the dielectric isolation process due to the high temperatures required for the process, as well as the mechanical grinding and polishing necessary to form the silicon wafer. Because the grinding and polishing steps have such a wide range of accuracy, this requirement of the process results in a wide tolerance of island thicknesses. With respect to the high temperatures of the DI process, stress can result in the islands, as well as warpage of the silicon wafer during the high temperature operations.
A more recent approach to producing dielectrically isolated bipolar devices uses bonded wafer technology. The present bonded wafer process includes the bonding together of one wafer having an epitaxial layer thereon with a second wafer having an oxide layer thereon. The first wafer is removed after bonding, leaving the epitaxial layer bound to the oxide surface, resulting in a basic SOI structure. Prior to the bonding, a buried layer can be formed by diffusing dopants into the epitaxial layer.
This bonding technique, while having the advantages of reducing wafer warpage and island stress, has the other disadvantages similar to the conventional DI. Because of the high temperature heating required during the bonding process, the diffusion time of the dopants is increased, particularly in the buried layer. This in turn reduces the sharpness of the doping profile at the first wafer and epitaxial layer interface, thereby reducing the accuracy of electrochemical/mechanical removal of the first wafer. Another disadvantage of the bonding process is that in order to align the buried layers which are diffused from the back side with the patterns of the front side, special alignment marks are required. These necessary marks may be formed by etching vias in the silicon and then filling the same with polycrystalline silicon. The formation of these marks adds to the difficulty in forming the bonded wafer structure, as well as provides potential unbonded sites.
It is therefore an object of the present invention to provide a new and improved complementary device in integrated circuits.
It is another object of the present invention to provide a new and improved bonded wafer fabrication process.
It is further an object of the present invention to provide a new and improved method for forming a buried layer in a bonded wafer.
It is still another object of the present invention to provide new and improved semiconductor devices having smaller dimensions and faster operating response.
These and other objects of the present invention are attained by providing a method of forming a semiconductor silicon on insulator (SOI) device which forms a buried layer after the actual bonding has been completed. In accordance with a preferred embodiment of the invention, a complementary bipolar SOI device is formed by initially forming a first epitaxial layer on a heavily doped substrate followed by bonding an oxidized handle wafer to the epitaxial layer. The original substrate is then ground, etched and polished away, resulting in a basic SOI structure. A conductive buried layer is then formed in the first epitaxial layer. In a preferred embodiment, this conductive layer may be formed by heavily diffusing N and P type dopants in designated N+ and P+ regions. A second epitaxial layer of N-type conductivity is then deposited over the N+ and P+ regions. The region over the P+ conductive region is then patterned and P type dopants are introduced from the front side of the wafer. This results in a light doped N region being formed over the N+ conductive buried region and light doped P region being formed over the P+ conductive buried region.
Since the conductive buried layers are formed after the bonding process, the heating during bonding will not effect the diffusion of the dopants in these layers. Thus, as a result of the invention, not only are P-type buried layers made possible, but the conductive buried layers will not tend to diffuse toward the surface. This reduction in up diffusion results in eliminating the need for the deeper tubs or wells of the conventional bonded wafers, thereby resulting in devices of smaller dimensions.
Also as a result of the invention, thinner islands can be produced. In the conventional dielectric isolation or bonded wafer technology, the thickness of the devices, e.g., the distance between the conductive buried layer and the collector-base junction, depends upon the grinding, etching and polishing technology. Therefore, the thickness tolerance is relatively large, which has a degrading effect on the performance of the devices. In accordance with present invention, the device is built entirely in a second epitaxial layer. As a result, the thickness of the device forming layer is dependent on the thickness of the second epitaxial layer which has a significantly better thickness tolerance than that associated with the conventional dielectric isolation process. Therefore, the present invention can produce much thinner islands and, consequently, smaller devices.
Additionally, because the diffusion is performed from the front side, alignment marks from the back side are not necessary. The diffused areas for the conductive buried layer actually provide noticeable unevenness on the surface as a result of the dopants being added. This unevenness is transferred to the second epitaxial layer, thereby providing noticeable aligning indicators for the subsequent doping of the second epitaxial layer. As a result of not requiring the alignment marks of the convention bonded wafer, the manufacturing of the bonded wafer is made easier and more reliable.